amd cpu&gpu 討論post #39 睇#1&有時間幫手填表

TSMC Q4: 7nm Dominates Revenue, Preps 5nm Ramp, 6nm By EOY



N6
Last year, TSMC announced the N6 node. This is an EUV-based node, but unlike N7+ which is entering its 2nd year of production, N6 is designed to be the easy migration path from N7 as its design rules are fully compatible with N7. In fact, TSMC considers N6 to be part of the “N7 family”. N6 is said to provide around 15-20% higher density with improved power consumption compared to N7, albeit no iso-power or speed comparisons where provided. We believe the density gains are obtained from switching from double diffusion breaks to a single isolation line. TSMC did note that N6 has 1 more EUV layer compared to N7+. TSMC reported that N6 is on track for risk production in the first quarter of this year with volume production expected before the end of the year. The 7 nm family is expected to continue to contribute more than 30% of wafer revenue in 2020.

N5
The N5 node is the next full node after N7 for TSMC. It features an 80% density improvement and a 20% speed gain. This process uses EUV extensively and is on track for volume production in the first half of this year. It’s worth noting that at the earnings call, Dr. C.C. Wei. TSMC CEO said “first half of this year” for the N5 ramp while saying “first quarter of this year” for the N6 risk production. This implies N5 ramp might be in Q2 rather than Q1. “We expect a very fast and smooth ramp-up in the second half of the year driven by both mobile and HPC applications, ” Wei said. “We are confident that 5-nanometer will be another large and long-lasting node for TSMC,” he added. TSMC expects N5 to contribute about 10% of total wafer revenue in 2020. Compared to the initial N7 ramp, at a similar point in the development cycle to where N5 is today, TSMC is reporting slightly fewer tape-outs on its N5, however, they expect the high-volume tape-outs to be comparable.

N3
Like N5, the N3 node is the next full node after N5 for TSMC. Wei stated that N3 will offer another full-node scaling benefit in terms of performance, power, and area compared to N5. “We are working with customers on N3 designs and the technology progress is going well. We have many technology options in development and we carefully evaluate all the different approaches. Our decisions are based on technology maturity, performance, and cost,” Wei said. “We expect our N3 technology to be the most advanced foundry technology in both PPA and transistor technology when introduced.” Given 2021 has the N5P process planned, we expect TSMC N3 to ramp around the 2022-23 timeframe.

https://fuse.wikichip.org/news/3227/tsmc-q4-7nm-dominates-revenue-preps-5nm-ramp-6nm-by-eoy/

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